Abstract

Prediction of accurate values for insertion loss (S₂₁)  on printed circuit boards has become ever more critical to SI modeling as signal speeds required for next-generation networking equipment move into the 10+ GHz range. Existing industry-standard insertion loss estimation techniques assume that the copper conductors (PCB traces) are smooth, when in fact they are not. The error thus induced is less significant at lower speeds, but cannot be ignored at frequencies above a few GHz. Accurate estimation of PCB laminate dissipation factor (Df) is another goal integral to SI modeling. Industry-standard methods again assume the smooth copper case, with consequent frequency-dependent error introduced into extracted values of Df. This paper describes a set of stripline PCB test vehicles used to correlate copper trace surface roughness to insertion loss. The main errors induced in extracted values of Df resulting from increased conductor losses due to surface roughness have been analyzed.

1. Introduction
2. Copper Surface Texture in PCB Manufacture
3. Description of PCB Test Vehicle
4. Description of Test Equipment and Technique
5. Measurement Results--Total Loss
6. Relative Influence of Foil Type and Surface Treatment Type
7. Effect of Roughness on Modeled Conductor Loss (α_c)
8 Extraction of Df using Corrected α_c and Induced Error in Df Values
9. Follow-on Work

Introduction

Increasing on-board signal speeds in the telecom industry, in some cases exceeding 10 GHz, are driving the need for leading-edge network infrastructure products to move away from conventional FR-4 laminates. The main reason for this is that the dissipation factor (Df) of such materials is rapidly becoming inadequate to maintain required levels of signal integrity.

Total loss, as physically measured on a Vector Network Analyzer (VNA) or other instrument, comprises the sum of conductor loss (α_c) and dielectric loss (α_d ). The property of interest, Df, is derived solely from the dielectric loss term. It is not possible in practical terms to make separate and independent measurements of α_c or α_d. For this reason, the existing industry-standard Df extraction algorithms call for an empirical estimation of the value of α_c, which is subtracted from the measured total loss, thus yielding the value of α_d from which Df can then be derived.

A known defect of the existing algorithms is that they assume that the copper conductor (trace) is perfectly smooth. At typical PCB trace dimensions (75-175 µm wide and 15-35µm thick), and at speeds below 1 GHz, the effect of surface roughness upon the error in Df is small. However as frequencies approach 10 GHz; the skin effect region becomes sufficiently shallow so as to drive a significant fraction of the current flow into the surface texture features, thus resulting in an actual value of α_c which is considerably higher than that modeled in the smooth copper case.

This paper describes insertion loss measurements performed on a 3x3 matrix of balanced single-stripline test vehicles differing only in the degree of roughness of the inner-layer copper foil. The factors that affect the surface roughness are the inherent roughness of the foil itself, and the surface-treatment-induced roughness intended to enhance inner-layer adhesion. The matrix allows for relative weighting of these two contributions to roughness for each test sample. All other relevant variables, such as the PCB stackup (glass cloth style and resin content), trace dimensions and dielectric thickness, were kept constant. This was done so that any measured differences in a c would originate only from the varying surface textures of the inner-layer traces.

The effect exerted by deviation from ideal a c upon extracted values of Df is also demonstrated in this paper. In the worst (roughest surface) case, the assumption of a perfectly smooth copper trace results in a Df deviation of nearly 50% from the result calculated using our preferred algorithm.

Copper Surface Texture in PCB Manufacture

Smooth copper is never used in actual practice, though it would be theoretically possible to manufacture a multilayer PCB using inner-layer copper with a very close to perfectly smooth finish. In the case of a mirror-bright surface, foil-to-resin adhesion would be compromised, thus increasing the propensity of the board to delaminate during the thermal stresses of the PCB assembly process.